View AD60506_1206048.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Dual, Low Noise, Single-Supply Variable Gain Amplifier AD605
FEATURES
2 independent linear-in-dB channels Input noise at maximum gain: 1.8 nV/Hz, 2.7 pA/Hz Bandwidth: 40 MHz (-3 dB) Differential input Absolute gain range programmable -14 dB to +34 dB (FBK shorted to OUT) through 0 dB to 48 dB (FBK open) Variable gain scaling: 20 dB/V through 40 dB/V Stable gain with temperature and supply variations Single-ended unipolar gain control Output common mode independently set Power shutdown at lower end of gain control Single 5 V supply Low power: 90 mW/channel Drives ADCs directly
VGN
FUNCTIONAL BLOCK DIAGRAM
GAIN CONTROL AND SCALING PRECISION PASSIVE INPUT ATTENUATOR FIXED GAIN AMPLIFIER +34.4dB OUT FBK
VREF
VOCM +IN -IN DIFFERENTIAL ATTENUATOR 0 TO -48.4dB
Figure 1.
APPLICATIONS
Ultrasound and sonar time-gain controls High performance AGC systems Signal measurement
GENERAL DESCRIPTION
The AD605 is a low noise, accurate, dual channel, linear-in-dB variable gain amplifier, optimized for any application requiring high performance, wide bandwidth variable gain control. Operating from a single 5 V supply, the AD605 provides differential inputs and unipolar gain control for ease of use. Added flexibility is achieved with a user-determined gain range and an external reference input that provides user-determined gain scaling (dB/V). The high performance linear-in-dB response of the AD605 is achieved with the differential input, single-supply, exponential amplifier (DSX-AMP) architecture. Each of the DSX-AMPs comprise a variable attenuator of 0 dB to -48.4 dB followed by a high speed fixed gain amplifier. The attenuator is based on a 7-stage R-1.5R ladder network. The attenuation between tap points is 6.908 dB, and 48.360 dB for the entire ladder network. The DSX-AMP architecture results in 1.8 nV/Hz input noise spectral density and accepts a 2.0 V input signal when VOCM is biased at VP/2. Each independent channel of the AD605 provides a gain range of 48 dB that can be optimized for the application. Gain ranges between -14 dB to +34 dB and 0 dB to +48 dB can be selected by a single resistor between Pin FBK and Pin OUT. The lower and upper gain ranges are determined by shorting Pin FBK to Pin OUT, or leaving Pin FBK unconnected, respectively. The two channels of the AD605 can be cascaded to provide 96 dB of very accurate gain range in a monolithic package. The gain control interface provides an input resistance of approximately 2 M and scale factors from 20 dB/V to 30 dB/V for a VREF input voltage of 2.5 V to 1.67 V, respectively. Note that scale factors up to 40 dB/V are achievable with reduced accuracy for scales above 30 dB/V. The gain scales linearly in dB with control voltages (VGN) of 0.4 V to 2.4 V for the 20 dB/V scale and 0.20 V to 1.20 V for the 40 dB/V scale. When VGN is <50 mV, the amplifier is powered down to draw 1.9 mA. Under normal operation, the quiescent supply current of each amplifier channel is only 18 mA. The AD605 is available in 16-lead PDIP and 16-lead SOIC_N and is guaranteed for operation over the -40C to +85C temperature range.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
00541-001
AD605
AD605 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics (per Channel) ................... 7 Theory of Operation ...................................................................... 13 Differential Ladder (Attenuator).............................................. 14 AC Coupling ............................................................................... 14 Gain Control Interface............................................................... 14 Active Feedback Amplifier (Fixed Gain Amp) ...................... 15 Applications..................................................................................... 16 Connecting Two Amplifiers to Double the Gain Range....... 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19
REVISION HISTORY
1/06--Rev. C to Rev. D Updated Format..................................................................Universal Changes to Table 2............................................................................ 5 Changes to the Differential Ladder (Attenuator) Section......... 14 Updated the Outline Dimensions ................................................ 18 Changes to the Ordering Guide.................................................... 19 7/04--Rev. B to Rev. C Edits to General Description........................................................... 1 Edits to Specifications ...................................................................... 2 Edits to Ordering Guide .................................................................. 3 Change to TPC 22............................................................................. 6 Updated Outline Dimensions ....................................................... 12
Rev. D | Page 2 of 20
AD605 SPECIFICATIONS
Each channel @ TA = 25C, VS = 5 V, RS = 50 , RL = 500 , CL = 5 pF, VREF = 2.5 V (scaling = 20 dB/V), -14 dB to +34 dB gain range, unless otherwise noted. Table 1.
Parameter INPUT CHARACTERISTICS Input Resistance Input Capacitance Peak Input Voltage Input Voltage Noise Input Current Noise Noise Figure Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS -3 dB Bandwidth Slew Rate Output Signal Range Output Impedance Output Short-Circuit Current Harmonic Distortion HD2 HD3 HD2 HD3 Two-Tone Intermodulation Distortion (IMD) Conditions Min AD605A Typ 175 40 3.0 2.5 2.5 1.8 2.7 8.4 12 -20 40 170 2.5 1.5 2 40 -64 -68 -51 -53 Max Min AD605B Typ 175 40 3.0 2.5 2.5 1.8 2.7 8.4 12 -20 40 170 2.5 1.5 2 40 -64 -68 -51 -53 Max Unit pF V nV/Hz pA/Hz dB dB dB MHz V/s V mA dBc dBc dBc dBc
At minimum gain VGN = 2.9 V VGN = 2.9 V RS = 50 , f = 10 MHz, VGN = 2.9 V RS = 200 , f = 10 MHz, VGN = 2.9 V f = 1 MHz, VGN = 2.65 V Constant with gain VGN = 1.5 V, Output = 1 V step RL 500 f = 10 MHz VGN = 1 V, VOUT = 1 V p-p f = 1 MHz f = 1 MHz f = 10 MHz f = 10 MHz RS = 0 , VGN = 2.9 V, VOUT = 1 V p-p f = 1 MHz f = 10 MHz f = 10 MHz, VGN = 2.9 V, output referred f = 10 MHz, VGN = 2.9 V, VOUT = 1 V p-p, input referred Ch1: VGN = 2.65 V, inputs shorted, Ch2: VGN = 1.5 V (mid gain), f = 1 MHz, VOUT = 1 V p-p 1 MHz < f < 10 MHz, full gain range
1 dB Compression Point Third-Order Intercept Channel-to-Channel Crosstalk
-72 -60 +15 -1 -70
-72 -60 +15 -1 -70
dBc dBc dBm dBm dB
Group Delay Variation VOCM Input Resistance ACCURACY Absolute Gain Error -14 dB to -11 dB -11 dB to +29 dB +29 dB to +34 dB Gain Scaling Error Output Offset Voltage Output Offset Variation
2.0 45
2.0 45
ns k
0.25 V < VGN < 0.40 V 0.40 V < VGN < 2.40 V 2.40 V < VGN < 2.65 V 0.4 V < VGN < 2.4 V VREF = 2.500 V, VOCM = 2.500 V VREF = 2.500 V, VOCM = 2.500 V
-1.2 -1.0 -3.5 -50
+1.0 0.3 -1.25 0.25 30 30
+3.0 +1.0 +1.2 +50 95
-1.2 -1.0 -3.5 -50
+0.75 0.2 -1.25 0.25 30 30
+3.0 +1.0 +1.2 +50 50
dB dB dB dB/V mV mV
Rev. D | Page 3 of 20
AD605
Parameter GAIN CONTROL INTERFACE Gain Scaling Factor Gain Range Input Voltage (VGN) Range Input Bias Current Input Resistance Response Time POWER SUPPLY Supply Voltage Power Dissipation VREF Input Resistance Quiescent Supply Current Power Down Power-Up Response Time Power-Down Response Time Conditions VREF = 2.5 V, 0.4 V < VGN < 2.4 V VREF = 1.67 V FBK short to OUT FBK open 20 dB/V, VREF = 2.5 V Min 19 AD605A Typ 20 30 -14 to +34 0 to 48 0.1 to 2.9 -0.4 2 0.2 5.0 90 10 18 1.9 0.6 0.4 Max 21 Min 19 AD605B Typ 20 30 -14 to +34 0 to 48 0.1 to 2.9 -0.4 2 0.2 5.0 90 10 18 1.9 0.6 0.4 Max 21 Unit dB/V dB/V dB dB V A M s V mW k mA mA s s
48 dB gain change 4.5
5.5
4.5
5.5
VPOS VPOS, VGN < 50 mV 48 dB gain, VOUT = 2 V p-p
23 3.0
23 3.0
Rev. D | Page 4 of 20
AD605 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage +VS Pin 12, Pin 13 (with Pin 4, Pin 5 = 0 V) Input Voltage Pin 1 to Pin 3, Pin 6 to Pin 9, Pin 16 Internal Power Dissipation 16-Lead PDIP 16-Lead SOIC_N Operating Temperature Range Storage Temperature Range Lead Temperature, Soldering 60 sec Thermal Resistance JA 16-Lead PDIP 16-Lead SOIC_N Rating 6.5 V VPOS, 0 1.4 W 1.2 W -40C to +85C -65C to +150C 300C 85C/W 100C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. D | Page 5 of 20
AD605 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VGN1 1 -IN1 2 +IN1 3 GND1 4 16 VREF 15 OUT1 14 FBK1
13 VPOS TOP VIEW GND2 5 (Not to Scale) 12 VPOS +IN2 6 -IN2 7 VGN2 8 11 FBK2
00541-002
AD605
10 OUT2 9 VOCM
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VGN1 -IN1 +IN1 GND1 GND2 +IN2 -IN2 VGN2 VOCM OUT2 FBK2 VPOS VPOS FBK1 OUT1 VREF Description CH1 Gain-Control Input and Power-Down Pin. If grounded, device is off; otherwise, positive voltage increases gain. CH1 Negative Input. CH1 Positive Input. Ground. Ground. CH2 Positive Input. CH2 Negative Input. CH2 Gain-Control Input and Power-Down Pin. If grounded, device is off; otherwise, positive voltage increases gain. Input to This Pin Defines Common-Mode Voltage for OUT1 and OUT2. CH2 Output. Feedback Pin That Selects Gain Range of CH2. Positive Supply. Positive Supply. Feedback Pin That Selects Gain Range of CH1. CH1 Output. Input to This Pin Sets Gain Scaling for Both Channels: 2.5 V = 20 dB/V, and 1.67 V = 30 dB/V.
Rev. D | Page 6 of 20
AD605 TYPICAL PERFORMANCE CHARACTERISTICS (PER CHANNEL)
VREF = 2.5 V (20 dB/V scaling), f = 1 MHz, RL = 500 , CL = 5 pF, TA = 25C, VSS = 5 V.
40
40.0 37.5
30
THEORETICAL
-40C, +25C, +85C
35.0
20
GAIN SCALING (dBV)
32.5 ACTUAL 30.0 27.5 25.0
GAIN (dB)
10
0
-10
00541-003
-20
0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
2.9
20.0 1.25
1.50
1.75 VREF (V)
2.00
2.25
2.50
Figure 3. Gain vs. VGN
3.0
Figure 6. Gain Scaling vs. VREF
50 40
GAIN ERROR (dB)
2.5 2.0 1.5
30
GAIN (dB)
FBK (OPEN)
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
-40C
20 FBK (SHORT) 10 0 -10 -20 0.1
+25C +85C
00541-004
-2.5 -3.0 0.2 0.7 1.2
VGN (V)
1.7
2.2
2.7
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
2.9
Figure 7. Gain Error vs. VGN at Three Temperatures
2.0
Figure 4. Gain vs. VGN for Different Gain Ranges
40
1.5
30 ACTUAL 20 30dB/V (VREF = 1.67V)
GAIN ERROR (dB)
ACTUAL
1.0 f = 1MHz 0.5 0 f = 5MHz -0.5 -1.0
00541-008
GAIN (dB)
10
20dB/V (VREF = 2.50V)
f = 10MHz
0
-10
00541-005
-1.5 -2.0
-20
0.2
0.7
1.2 VGN (V)
1.7
2.2
2.7
0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
2.9
Figure 8. Gain Error vs. VGN at Three Frequencies
Figure 5. Gain vs. VGN for Different Gain Scalings
Rev. D | Page 7 of 20
00541-007
00541-006
22.5
AD605
2.0 1.5 1.0
GAIN ERROR
60
VGN = 2.9V (FBK = OPEN)
40
VGN = 2.9V (FBK = SHORT) VGN = 1.5V (FBK = OPEN)
0.5 0 -0.5 -1.0 30dB/V VREF = 1.67V
GAIN (dB)
20dB/V VREF = 2.50V
20
VGN = 1.5V (FBK = SHORT) VGN = 0.1V (FBK = OPEN) VGN = 0.1V (FBK = SHORT)
0
-20
00541-009
-2.0 0.2
0.7
1.2 VGN (V)
1.7
2.2
2.7
-60 100k
1M 10M FREQUENCY (Hz)
100M
Figure 9. Gain Error vs. VGN for Two Gain Scale Values
20 18 16 14
Figure 12. AC Response for Three Values of VGN
2.525
N = 50 G(dB) = G(CH1) - G(CH2)
2.520 2.515 2.510
VOS (V)
VOCM = 2.50V -40C
+25C
PERCENTAGE
12 10 8 6 4 2 0 -0.8 -0.6 -0.4 -0.2 0 0.2 DELTA GAIN (dB) 0.4 0.6 0.8
00541-010
2.505 2.500 2.495 2.490 2.485 2.480 2.475 0 0.5 1.0 1.5 VGN (V) 2.0 2.5
00541-014
+85C
3.0
Figure 10. Gain Match, VGN1 = VGN2 = 1.0 V
20 18 16 14
NOISE (nV/ Hz) PERCENTAGE N = 50 G(dB) = G(CH1) - G(CH2)
Figure 13. Output Offset vs. VGN at Three Temperatures
130 125 120 +25C 115 110 105 100
00541-011 00541-015
+85C
12 10 8 6 4 2 0 -0.8 -0.6 -0.4 -0.2 0 0.2 DELTA GAIN (dB) 0.4 0.6 0.8
-40C
95 90 0
0.5
1.0
1.5 VGN (V)
2.0
2.5
3.0
Figure 11. Gain Match, VGN1 = VGN2 = 2.50 V
Figure 14. Output Referred Noise vs. VGN at Three Temperatures
Rev. D | Page 8 of 20
00541-013
-1.5
-40
VGN = 0.0V
AD605
1000
100 VGN = 2.9V
NOISE (nV/ Hz)
NOISE (nV/ Hz)
100
10
10
1.0
RSOURCE ALONE
1 0.1
00541-016
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
2.9
0.1 1
10 RSOURCE ()
100
1k
Figure 15. Input Referred Noise vs. VGN
2.00 VGN = 2.9V 1.95
25 30
Figure 18. Input Referred Noise vs. RSOURCE
VGN = 2.9V
1.90
NOISE (nV/ Hz)
1.85 1.80 1.75 1.70
NOISE FIGURE (dB)
20
15
10
00541-017
00541-020
1.65 1.60 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
5 1
10 RSOURCE ()
100
1k
TEMPERATURE (C)
Figure 16. Input Referred Noise vs. Temperature
1.90 VGN = 2.9V 1.85
50 60
Figure 19. Noise Figure vs. RSOURCE
RS = 50
NOISE FIGURE (dB)
NOISE (nV/ Hz)
1.80
40
1.75
30
1.70
20
1.65
00541-018
10
00541-021
1.60 100k
1M FREQUENCY (Hz)
10M
0 0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
2.9
Figure 17. Input Referred Noise vs. Frequency
Figure 20. Noise Figure vs. VGN
Rev. D | Page 9 of 20
00541-019
AD605
-30 -35 VOUT = 1V p-p VGN = 1.0V
15 10 5 INPUT GENERATOR LIMIT = 21dBm
HARMONIC DISTORTION (dBc)
-40 -45 -50 -55 -60
00541-022
PIN (dBm)
0 -5 -10 -15 -20 0.1 FREQ = 10MHz FREQ = 1MHz 0.5 0.9 1.3 1.7 VGN (V) 2.1 2.5
HD3 HD2
-70 100k
1M
10M FREQUENCY (Hz)
100M
2.9
Figure 21. Harmonic Distortion vs. Frequency
-35 -40
HARMONIC DISTORTION (dBc)
35
Figure 24. 1 dB Compression vs. VGN
VOUT = 1V p-p 30
-45 -50 -55 -60 -65 HD2 (1MHz) HD2 (10MHz)
HD3 (10MHz)
INTERCEPT (dBm)
25 f = 1MHz 20 f = 10MHz 15 10 5
00541-023
00541-026
-70 -75 0.5
HD3 (1MHz) 0.8 1.1 1.4 1.7 VGN (V) 2.0 2.3 2.6
0 -5 0.6
2.9
1.0
1.4
1.8 VGN (V)
2.2
2.6
3.0
Figure 22. Harmonic Distortion vs. VGN at 1 MHz and 10 MHz
-20 -30 -40 -50
-400mV/DIV
Figure 25. Third-Order Intercept vs. VGN at 1 MHz and 10 MHz
2V
f = 10MHz VOUT = 1V p-p VGN = 1.0V
VOUT = 2V p-p VGN = 1.5V
POUT (dBm)
-60 -70 -80 -90 -100
00541-024
TRIG'D
00541-027
-110 -120 9.92 9.96 10.00 10.02 FREQUENCY (MHz)
10.04
2V 253ns
100ns/DIV
1.253s
Figure 23. Intermodulation Distortion
Figure 26. Large Signal Pulse Response
Rev. D | Page 10 of 20
00541-025
-65
AD605
200 VOUT = 200mV p-p VGN = 1.5V
-30 VGN1 = 1V VOUT1 = 1V p-p VIN2 = GND
-40
CROSSTALK (dB)
-50 VGN2 = 2.9V -60
40mV (DIV)
-70 VGN2 = 2.5V -80 VGN2 = 2.0V VGN2 = 0.1V 1M 10M FREQUENCY (Hz)
00541-031
TRIG'D
00541-028
-200 253ns
100ns/DIV
1.253s
-90 100k
100M
Figure 27. Small Signal Pulse Response
Figure 30. Crosstalk (CH1 to CH2) vs. Frequency for Four Values of VGN2
0
500mV 2.9V
VIN = 0dBm -10
100 90
VGN = 2.9V -20
CMRR (dB)
VGN = 2.5V -30
VGN (V)
-40
10 0%
VGN = 2.0V VGN = 0.1V
-50
500mV 200ns
00541-029
0.0V
-60 100k
1M 10M FREQUENCY (Hz)
100M
Figure 28. Power-Up/Power-Down Response
Figure 31. Common-Mode Rejection Ratio (CMRR) vs. Frequency for Four Values of VGN
180 VGN = 2.9V 175 170 165 160 155 150
00541-033
500mV 2.9V
100
10 0%
INPUT IMPEDANCE ()
90
VGN (V)
0.1V 500mV 100ns
00541-030
145 140 100k
1M 10M FREQUENCY (Hz)
100M
Figure 29. Gain Response
Figure 32. Input Impedance vs. Frequency
Rev. D | Page 11 of 20
00541-032
AD605
25 +IS (AD605) 20
SUPPLY CURRENT (mA)
GROUP DELAY (ns)
16
14
12
15
10
10
8
VGN = 0.1V
50
00541-034
VGN = 2.9V 4 100k 1M 10M FREQUENCY (Hz)
0 -40 -30 -20 -10
0
10 20 30 40 50 TEMPERATURE (C)
60
70
80
90
100M
Figure 33. Supply Current (One Channel) vs. Temperature
Figure 34. Group Delay vs. Frequency
Rev. D | Page 12 of 20
00541-035
+IS (VGN = 0)
6
AD605 THEORY OF OPERATION
The AD605 is a dual channel, low noise variable gain amplifier. Figure 35 shows the simplified block diagram of one channel. Each channel consists of a single-supply X-AMP(R) (hereafter called DSX, differential single-supply X-AMP) comprised of: * * * * Precision passive attenuator (differential ladder) Gain control block VOCM buffer with supply splitting resistors R3 and R4 Active feedback amplifier 1 (AFA) with gain setting resistors R1 and R2 The desired gain can then be achieved by setting the unipolar gain control (VGN) to a voltage within its nominal operating range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is monotonic for a complete gain control range of 0.1 V to 2.9 V. Maximum gain can be achieved at a VGN of 2.9 V. Because the two channels are identical, only Channel 1 is used to describe their operation. VREF and VOCM are the only inputs that are shared by the two channels, and because they are normally ac grounds, crosstalk between the two channels is minimized. For highest gain scaling accuracy, VREF should have an external low impedance voltage source. For low accuracy 20 dB/V applications, the VREF input can be decoupled with a capacitor to ground. In this mode, the gain scaling is determined by the midpoint between +VCC and GND; therefore, care should be taken to control the supply voltage to 5 V. The input resistance looking into the VREF pin is 10 k 20%. The AD605 is a single-supply circuit and the VOCM pin is used to establish the dc level of the midpoint of this portion of the circuit. VOCM needs only an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 V, GND). However, if the dc level of the output is important to the user (see the Applications section of the AD9050 data sheet for an example), then VOCM can be specifically set. The input resistance looking into the VOCM pin is 45 k 20%.
1
The linear-in-dB gain response of the AD605 can generally be described by Equation 1. G (dB) = (Gain Scaling (dB/V)) x (Gain Control (V)) - (19 dB - (14 dB) x (FB)) (1) where: FB = 0, if FBK-to-OUT are shorted. FB = 1, if FBK-to-OUT is open. Each channel provides between -14 dB to +34.4 dB through 0 dB to +48.4 dB of gain depending on the value of the resistance connected between Pin FBK and Pin OUT. The center 40 dB of gain is exactly linear-in-dB while the gain error increases at the top and bottom of the range. The gain is set by the gain control voltage (VGN). The VREF input establishes the gain scaling. The useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF voltage of 2.5 V and 1.25 V, respectively. For example, if FBK to OUT were shorted and VREF were set to 2.50 V (to establish a gain scaling of 20 dB/V), the gain equation would simplify to G (dB) = (20 (dB/V)) x (VGN (V)) - 19 dB (2)
To understand the active-feedback amplifier topology, refer to the AD830 data sheet. The AD830 is a practical implementation of the idea.
VREF VGN +IN C1 EXT 175
GAIN CONTROL DISTRIBUTED GM DIFFERENTIAL ATTENUATOR + G1 + Ao 175 R2 20 R1 820
00541-036
C2 -IN VPOS R3 200k VOCM C3 EXT R4 200k
OUT 3.36k FBK
G2 +
+
Figure 35. Simplified Block Diagram of a Single Channel of the AD605
Rev. D | Page 13 of 20
AD605
+IN R -6.908dB 1.5R MID R 1.5R R 1.5R R 1.5R R 1.5R R 1.5R R 1.5R R 1.5R 175
00541-037
R
-13.82dB 1.5R
R
-20.72dB 1.5R
R
-27.63dB 1.5R
R
-34.54dB 1.5R
R
-41.45dB 1.5R
R
-48.36dB 1.5R 175
-IN
NOTE: R = 96 1.5R = 144
Figure 36. R-1.5R Dual Ladder Network
DIFFERENTIAL LADDER (ATTENUATOR)
The attenuator before the fixed gain amplifier is realized by a differential 7-stage R-1.5R resistive ladder network with an untrimmed input resistance of 175 single-ended or 350 differentially. The signal applied at the input of the ladder network is attenuated by 6.908 dB per tap; thus, the attenuation at the first tap is 6.908 dB, at the second, 13.816 dB, and so on all the way to the last tap where the attenuation is 48.356 dB (see Figure 36). A unique circuit technique is used to interpolate continuously between the tap points, thereby providing continuous attenuation from 0 dB to -48.36 dB. One can think of the ladder network together with the interpolation mechanism as a voltage-controlled potentiometer. Since the DSX is a single-supply circuit, some means of biasing its inputs must be provided. Node MID together with the VOCM buffer performs this function. Without internal biasing, external biasing is required. If not done carefully, the biasing network can introduce additional noise and offsets. By providing internal biasing, the user is relieved of this task and only needs to ac couple the signal into the DSX. It should be made clear again that the input to the DSX is still fully differential if driven differentially, that is, Pin +IN and Pin -IN see the same signal but with opposite polarity. What changes is the load as seen by the driver; it is 175 when each input is driven single-ended, but 350 when driven differentially. This can be easily explained when thinking of the ladder network as two 175 resistors connected back-to-back with the middle node, MID, being biased by the VOCM buffer. A differential signal applied between nodes +IN and -IN results in zero current into node MID, but a single-ended signal applied to either input +IN or -IN, while the other input is ac grounded, causes the current delivered by the source to flow into the VOCM buffer via node MID. A feature of the X-AMP architecture is that the output-referred noise is constant vs. gain over most of the gain range. Referring to Figure 36, the tap resistance is approximately equal for all taps within the ladder, excluding the end sections. The resistance seen looking into each tap is 54.4 , which makes 0.95 nV/Hz of Johnson noise spectral density. Because there are two attenuators, the overall noise contribution of the ladder network is 2 times 0.95 nV/Hz or 1.34 nV/Hz, a large fraction of the total DSX noise. The rest of the DSX circuit components contribute another 1.20 nV/Hz, which together with the attenuator produces 1.8 nV/Hz of total DSX input, referred noise.
AC COUPLING
The DSX is a single-supply circuit; therefore, its inputs need to be ac-coupled to accommodate ground-based signals. External Capacitor C1 and Capacitor C2 in Figure 35 level shift the input signal from ground to the dc value established by VOCM (nominal 2.5 V). C1 and C2, together with the 175 looking into each of DSX inputs (+IN and -IN), act as high-pass filters with corner frequencies depending on the values chosen for C1 and C2. For example, if C1 and C2 are 0.1 F, then together with the 175 input resistance of each side of the differential ladder of the DSX, a -3 dB high-pass corner at 9.1 kHz is formed. If the DSX output needs to be ground referenced, then another ac coupling capacitor is required for level shifting. This capacitor also eliminates any dc offsets contributed by the DSX. With a nominal load of 500 and a 0.1 F coupling capacitor, this adds a high-pass filter with -3 dB corner frequency at about 3.2 kHz. The choice for all three of these coupling capacitors depends on the application. They should allow the signals of interest to pass unattenuated, while at the same time, they can be used to limit the low frequency noise in the system.
GAIN CONTROL INTERFACE
The gain control interface provides an input resistance of approximately 2 M at Pin VGN1 and gain scaling factors from 20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V, respectively. The gain varies linearly in dB for the center 40 dB of gain range, that is, for VGN equal to 0.4 V to 2.4 V for the 20 dB/V scale, and 0.25 V to 1.25 V for the 40 dB/V scale. Figure 37 shows the ideal gain curves when the FBK-to-OUT connection is shorted as described by the following equations: G (20 dB/V) = 20 x VGN - 19, VREF = 2.500 V G (30 dB/V) = 30 x VGN - 19, VREF = 1.6666 V G (40 dB/V) = 40 x VGN - 19, VREF = 1.250 V (3) (4) (5)
From the equations one can see that all gain curves intercept at the same -19 dB point; this intercept is 14 dB higher (-5 dB) if the FBK-to-OUT connection is left open. Outside of the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 dB of range. For a given gain scaling, one can calculate VREF as
VREF = 2.500 V x 20 dB/V Gain Scale
(6)
Rev. D | Page 14 of 20
AD605
40dB/V 35 30 25 20 15
GAIN (dB)
30dB/V
20dB/V
LINEAR-IN-dB RANGE OF AD605
10 5 0 -5
0.5
1.0
1.5
2.0
2.5
3.0
The AFA makes a differential input structure possible since one of its inputs (G1) is fully differential; this input is made up of a distributed gm stage. The second input (G2) is used for feedback. The output of G1 is some function of the voltages sensed on the attenuator taps that is applied to a high-gain amplifier (A0). Because of negative feedback, the differential input to the high gain amplifier is zero; this in turn implies that the differential input voltage to G2 times gm2 (the transconductance of G2) is equal to the differential input voltage to G1 times gm1 (the transconductance of G1). Therefore the overall gain function of the AFA is
VOUT VATTEN
00541-038
GAIN CONTROL VOLTAGE
-10 -15 -20
=
gm1 R1 x R2 x gm2 R2
(7)
Figure 37. Ideal Gain Curves vs. VREF
Usable gain control voltage ranges are 0.1 V to 2.9 V for the 20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN voltages of less than 0.1 V are not used for gain control because below 50 mV the channel is powered down. This can be used to conserve power and at the same time gate-off the signal. The supply current for a powered-down channel is 1.9 mA, and the response time to power the device on or off is less than 1 s.
where: VOUT is the output voltage. VATTEN is the effective voltage sensed on the attenuator. (R1 + R2)/R2 = 42. gm1/gm2 = 1.25; the overall gain is therefore 52.5 (34.4 dB). The AFA has additional features: inverting the output signal by switching the positive and negative input to the ladder network; the possibility of using the -IN input as a second signal input; and independent control of the DSX common-mode voltage. Under normal operating conditions, it is best to connect a decoupling capacitor to Pin VOCM, in which case, the commonmode voltage of the DSX is half of the supply voltage; this allows for maximum signal swing. Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be used as another signal input, the only limitation being the rather low slew rate of the VOCM buffer. If the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the DSX; again, this is done for level shifting and to eliminate any dc offsets contributed by the DSX (see the AC Coupling section). The gain range of the DSX is programmable by a resistor connected between Pin FBK and Pin OUT. The possible ranges are -14 dB to +34.4 dB when the pins are shorted together, or 0 dB to +48.4 dB when FBK is left open. Note that for the higher gain range, the bandwidth of the amplifier is reduced by a factor of five to about 8 MHz because the gain increased by 14 dB. This is the case for any constant gain bandwidth product amplifier that includes the active feedback amplifier.
ACTIVE FEEDBACK AMPLIFIER (FIXED GAIN AMP)
To achieve single-supply operation and a fully differential input to the DSX, an active feedback amplifier (AFA) was used. The AFA is an op amp with two gm stages; one of the active stages is used in the feedback path (therefore the name), while the other is used as a differential input. Note that the differential input is an open-loop gm stage that requires that it be highly linear over the expected input signal range. In this design, the gm stage that senses the voltages on the attenuator is a distributed one; for example, there are as many gm stages as there are taps on the ladder network. Only a few of them are on at any one time, depending on the gain control voltage.
Rev. D | Page 15 of 20
AD605 APPLICATIONS
The basic circuit in Figure 38 shows the connections for one channel of the AD605 with a gain range of -14 dB to +34.4 dB. The signal is applied at Pin 3. The ac coupling capacitors before Pin -IN1 and Pin +IN1 should be selected according to the required lower cutoff frequency. In this example, the 0.1 F capacitors, together with the 175 of each of the DSX input pins, provide a -3 dB high pass corner of about 9.1 kHz. The upper cutoff frequency is determined by the amplifier and is 40 MHz.
VGN 0.1F
1 2
VGN
C1 0.1F
1 2
VGN1 -IN1 +IN1 GND1 GND2 +IN2 -IN2 VGN2
VREF 16
2.500V R1
VIN C2 0.1F C3 0.1F
3 4 5 6 7
AD605
OUT1 15 FBK1 14
VPOS 13 VPOS 12 FBK2 11 OUT2 10 VOCM 9 R2
5V C5 0.1F OUT C6 0.1F
00541-040
C4 0.1F
8
VGN1 -IN1 +IN1 GND1 GND2 +IN2 -IN2 VGN2
VREF 16
2.500V OUT 0.1F 5V
Figure 39. Doubling the Gain Range with Two Amplifiers
VIN 0.1F
3 4 5 6 7 8
AD605
OUT1 15 FBK1 14
VPOS 13 VPOS 12 FBK2 11 OUT2 10
0.1F
Figure 38. Basic Connections for a Single Channel
As shown in Figure 38, the output is ac-coupled for optimum performance. In the case of connecting to the 10-bit, 40 MSPS ADC, AD9050, ac coupling can be eliminated as long as Pin VOCM is biased by the same 3.3 V common-mode voltage as the AD9050. Pin VREF requires a voltage of 1.25 V to 2.5 V, with gain scaling between 40 dB/V and 20 dB/V, respectively. Voltage VGN controls the gain; its nominal operating range is from 0.25 V to 2.65 V for 20 dB/V gain scaling, and 0.125 V to 1.325 V for 40 dB/V scaling. When this pin is taken to ground, the channel powers down and disables its output.
00541-039
VOCM 9
Two other easy combinations are possible to provide a gain range of -14 dB to +82.8 dB: make R1 a short and R2 an open, or make R1 an open and R2 a short. The bandwidth for both of these cases is dominated by the channel that is set to the higher gain and is about 8 MHz. From a noise standpoint, the second choice is the best because by increasing the gain of the first amplifier, the second amplifier's noise has less of an impact on the total output noise. One further observation regarding noise is that by increasing the gain, the output noise increases proportionally; therefore, there is no increase in signal-to-noise ratio. It actually stays fixed. It should be noted that by selecting the appropriate values of R1 and R2, any gain range between -28 dB to +68.8 dB and 0 dB to +96.8 dB can be achieved with the circuit in Figure 39. When using any value other than shorts and opens for R1 and R2, the final value of the gain range depends on the external resistors matching the on-chip resistors. Since the internal resistors can vary by as much as 20%, the actual values for a particular gain have to be determined empirically. Note that the two channels within one part match quite well; therefore, R1 tracks R2 in Figure 39. C3 is not required because the common-mode voltage at Pin OUT1 should be identical to the one at Pin +IN2 and Pin -IN2. However, since only 1 mV of offset at the output of the first DSX introduces an offset of 53 mV when the second DSX is set to the maximum gain of the lowest gain range (34.4 dB), and 263 mV when set to the maximum gain of the highest gain range (48.4 dB), it is important to include ac coupling to get the maximum dynamic range at the output of the cascaded amplifiers. C5 is necessary if the output signal needs to be referenced to any common-mode level other than half of the supply as is provided by Pin OUT2.
CONNECTING TWO AMPLIFIERS TO DOUBLE THE GAIN RANGE
Figure 39 shows the two channels of the AD605 connected in series to provide a total gain range of 96.8 dB. When R1 and R2 are shorts, the gain range is from -28 dB to +68.8 dB with a slightly reduced bandwidth of about 30 MHz. The reduction in bandwidth is due to two identical low-pass circuits being connected in series; in the case of two identical single-pole lowpass filters, the bandwidth would be reduced by exactly 2. If R1 and R2 are replaced by open circuits, that is, Pin FBK1 and Pin FBK2 are left unconnected, then the gain range shifts up by 28 dB to 0 dB to 96.8 dB. As previously noted, the bandwidth of each individual channel is reduced by a factor of 5 to about 8 MHz because the gain increased by 14 dB. In addition, there is still the 2 reduction because of the series connection of the two channels that results in a final bandwidth of the higher gain version of about 6 MHz.
Rev. D | Page 16 of 20
AD605
Figure 40 shows the gain vs. VGN for the circuit in Figure 39 at 1 MHz and the lowest gain range (-14 dB to +34.4 dB). Note that the gain scaling is 40 dB/V, double the 20 dB/V of an individual DSX; this is the result of the parallel connection of the gain control inputs, VGN1 and VGN2. One could of course also sequentially increase the gain by first increasing the gain of Channel 1 and then Channel 2. In this case, VGN1 and VGN2 are driven from separate voltage sources, for instance two separate DACs. Figure 41 shows the gain error of Figure 39.
80 70 60 50 40 ACTUAL f = 1MHz THEORETICAL 4 f = 1MHz 3 2
GAIN ERROR (dB)
1 0 -1 -2
00541-042
-3 -4 0.2
0.7
1.2 VGN (V)
1.7
2.2
2.7
Figure 41. Gain Error vs. VGN for the Circuit in Figure 39
GAIN (dB)
30 20 10 0 -10 -20 -30 -40 0.1 0.5 0.9 1.3 1.7 VGN (V) 2.1 2.5
00541-041
2.9
Figure 40. Gain vs. VGN for the Circuit in Figure 39
Rev. D | Page 17 of 20
AD605 OUTLINE DIMENSIONS
0.800 (20.32) 0.790 (20.07) 0.780 (19.81)
16 1 9
8
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 42. 16-Lead Plastic Dual In-Line Package [PDIP] (N-16) Dimensions shown in inches and (millimeters)
10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496)
16 1 9 8
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10
1.75 (0.0689) 1.35 (0.0531)
0.50 (0.0197) x 45 0.25 (0.0098)
8 0.51 (0.0201) SEATING 0.25 (0.0098) 0 1.27 (0.0500) 0.31 (0.0122) PLANE 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 43. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches)
Rev. D | Page 18 of 20
AD605
ORDERING GUIDE
Model AD605AN AD605ANZ 1 AD605AR AD605AR-REEL AD605AR-REEL7 AD605ARZ1 AD605ARZ-RL1 AD605ARZ-RL71 AD605BN AD605BR AD605BR-REEL AD605BR-REEL7 AD605BRZ1 AD605BRZ-RL1 AD605BRZ-RL71 AD605-EB AD605ACHIPS
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead PDIP 16-Lead PDIP 16-Lead SOIC_N 16-Lead SOIC_N, 13" Reel 16-Lead SOIC_N, 7" Reel 16-Lead SOIC_N 16-Lead SOIC_N, 13" Reel 16-Lead SOIC_N, 7" Reel 16-Lead PDIP 16-Lead SOIC_N 16-Lead SOIC_N, 13" Reel 16-Lead SOIC_N, 7" Reel 16-Lead SOIC_N 16-Lead SOIC_N, 13" Reel 16-Lead SOIC_N, 7" Reel Evaluation Board DIE
Package Option N-16 N-16 R-16 R-16 R-16 R-16 R-16 R-16 N-16 R-16 R-16 R-16 R-16 R-16 R-16
Z = Pb-free part.
Rev. D | Page 19 of 20
AD605 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00541-0-1/06(D)
Rev. D | Page 20 of 20

▲Up To Search▲

Price & Availability of AD60506

	To Download AD60506 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .